Date   : Wed, 21 Jan 1998 13:54:14 EST
From   : DDevenp666 <DDevenp666@...>
Subject: Re: BBC Emulator

In a message dated 1/20/98 11:26:38 GMT, you write:

<< I may be able to help here. A while back I had problems with xbeeb running
 Revs - the colour swap was slowly running up the screen. The problem
 eventually turned out to be the point at which the latches are reset.>>

It is Mode 4 at the top, a blanked bit of blue screen, then mode 5 at the
bottom.
Yes, it is scrolling upwards.
 
<< So, assume timer 1 is in continuous mode and is decrementing. The
interrupt
 occurs when the timer goes negative, not when it hits zero. At this point
 we see if we can generate an interrupt and the timer is reset from the
 latches.
 
 It's now that you need to know how the hardware works. When the timer is
 reset, the high order latch is transferred, then the low order latch. The
 same piece of hardware is used to do both resets (reduces production costs)
 but it means that the 6522 needs an extra cycle to perform the reset.
 
 To make things clearer, the xbeeb code looks like this:
 
 SystemViaTimer1 -= val;
 if ( SystemViaTimer1 < 0 )
 {
     if ( SystemViaTimer1Continuous )
     {
         SystemViaTimer1 += (SystemVia[T1LL] + 2 + 256 * SystemVia[T1LH]);
         SystemViaSetInterrupt ( INT_T1 );
     }
     else ...
 ....
 }
 
 What happens is this: Timer 1 crosses 0. We add the value of the latch.
 But because the hardware does this when the timer goes negative (ie
 time = -1) we have to add an extra 1. Then because the 6522 takes two
 cycles to reset the latches we have to add another 1.
 
 The total amount to be compensated is 2 cycles at 1MHz. If your emulator
 decrements counters at 2MHz and then corrects when they are read / written
 (like beebem) then you will have to add 4 cycles.  >>

Thanks for the pointer, it is on the right track...

I have taken into account the fact that the VIA's are slow devices (see the
old source release on the BBC Lives). Every read/write/event on the VIA is
already aligned to an even cycle of the 2MHz system clock. The problem seems
to lie with the screen drawing code! It is between 32 and 33 'ticks'
out every
vertical blank. Which corresponds to 6845 reg 4.

Cheers

Dave